IEC IEC62047-45 Edition1.02025-03 INTERNATIONAL STANDARD colour inside Semiconductordevices-Micro-electromechanicaldevices- Part45:SiliconbasedMEMSfabricationtechnology-Measurementmethodof impactresistanceofnanostructures IEC62047-45:2025-03(en) THISPUBLICATIONISCOPYRIGHTPROTECTED Copyright@2025IEC,Geneva,Switzerland or by any means,electronic or mechanical, including photocopying and microfilm,without permission in writing from either IEC or IEC's member National Committee in the country of the requester. If you have any questions about IEC copyright or have an enquiry about obtaining additional rights to this publication,please contact the address below or your local IEC member National Committee for further information. IEC Secretariat Tel.: +4122 919 02 11 3, rue de Varembe
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[email protected] IEC IEC62047-45 Edition1.02025-03 INTERNATIONAL STANDARD colour inside Semiconductordevices-Micro-electromechanicaldevices Part45:SiliconbasedMEMSfabricationtechnology-Measurementmethod of impactresistanceofnanostructures INTERNATIONAL ELECTROTECHNICAL COMMISSION ICS 31.080.99 ISBN 978-2-8327-0304-5 Warning!Make sure that you obtained this publication fromanauthorized distributor. Registered trademark of the International Electrotechnical Commission IEC62047-45:2025IEC2025 2 CONTENTS FOREWORD 3 Scope 1 5 2 Normativereferences 5 3 Termsanddefinitions 5 4 Requirements. 4.1 General.. 6 4.2 In situon-chiptesterdesign requirements.. 6 4.3 In-situ on-chiptesterfabrication requirements 9 4.4 Testing environment requirements.. 9 5 Testing method... 9 5.1 General. 9 5.2 Operationprocess 9 5.3 Nanostructure impactresistancetestingmethodoperationrequirements. 10 5.4 Nanostructureimpactresistancetestingmethodresultprocess.. 6 Test report.. 11 Annex A(informative)Exampleof thermal-drive in-situ on-chip nanostructure impact tester..... 12 A.1 General... 12 A.2 Designdimensions ofthetestingdevice.. 12 A.3 Microstructures bending strength test 14 Bibliography. 15 Figure1-Thein-situon-chipnanostructure impacttester Figure2-The three-viewdrawing of the in-situon-chiptester.. Figure3-Nanostructure impact resistance testing method operationprocess.. .10 Figure A.1-Scheme of the thermal-drive impact tester.. .12 Figure A.2-The three-view drawing of the thermal-drive impact tester. 13 FigureA.3-Testarea. 14 TableA.1-Dimensions fortesting device. 13 TableA.2-Microstructurebending strength test results. 14 - 3 - IEC62047-45:2025IEC2025 INTERNATIONALE ELECTROTECHNICALCOMMISS