论文标题
Pascal：抗SCA的时正式设计和验证流
PASCAL: Timing SCA Resistant Design and Verification Flow
论文作者
论文摘要
随着物联网的广泛采用，正在部署大量加密加速器。这些加速器和其他安全硬件IP具有安全性，这一点至关重要。安全性是一个额外的功能要求，因此许多安全验证工具不成熟。我们提出了一种方法/流程 - 该方法在RTL设计上起作用，并发现了潜在的计时侧通道攻击（SCA）漏洞。基于信息流分析，这能够识别可能导致信息泄漏的正时安全路径。该流程（自动）也消除了正时通道引起的信息泄漏。轻巧的补偿器块作为平衡或合规性FSM插入，以最小的修改来删除定时通道，而不会影响时钟周期时间或电路中关键路径的结合延迟。
A large number of crypto accelerators are being deployed with the widespread adoption of IoT. It is vitally important that these accelerators and other security hardware IPs are provably secure. Security is an extra functional requirement and hence many security verification tools are not mature. We propose an approach/flow-PASCAL-that works on RTL designs and discovers potential Timing Side-Channel Attack(SCA) vulnerabilities in them. Based on information flow analysis, this is able to identify Timing Disparate Security Paths that could lead to information leakage. This flow also (automatically) eliminates the information leakage caused by the timing channel. The insertion of a lightweight Compensator Block as balancing or compliance FSM removes the timing channel with minimum modifications to the design with no impact on the clock cycle time or combinational delay of the critical path in the circuit.
