论文标题
65nm CMO中的75kb SRAM用于基于内存计算的神经形态图像Denoising
A 75kb SRAM in 65nm CMOS for In-Memory Computing Based Neuromorphic Image Denoising
论文作者
论文摘要
本文介绍了用于图像denoising的内存计算（IMC）体系结构。拟议的基于SRAM的内存过程处理框架与神经形态视觉传感器产生的二进制图像的近似计算同时起作用。在TSMC 65NM工艺中实施，该拟议的体系结构可在与数字实施中相比，可节省2000倍的能源（来自IMC的222倍），与数字实施相比，与戴维斯传感器的视频录制进行了测试，并实现了1.25-1.66帧的峰值吞吐量。
This paper presents an in-memory computing (IMC) architecture for image denoising. The proposed SRAM based in-memory processing framework works in tandem with approximate computing on a binary image generated from neuromorphic vision sensors. Implemented in TSMC 65nm process, the proposed architecture enables approximately 2000X energy savings (approximately 222X from IMC) compared to a digital implementation when tested with the video recordings from a DAVIS sensor and achieves a peak throughput of 1.25-1.66 frames/us.
