论文标题
利用内存和内存不对称的杂种层中数据映射
Exploiting Inter- and Intra-Memory Asymmetries for Data Mapping in Hybrid Tiered-Memories
论文作者
论文摘要
现代计算系统正在包含包括DRAM和非易失性记忆（NVM）的混合记忆，以结合两种内存技术的最佳特性，达到低潜伏期，高可靠性和高密度。 DRAM-NVM混合记忆的一个突出特征是它的NVM访问延迟远高于DRAM访问延迟。我们称此内存不对称。我们观察到，长位寄生成分是DRAM和NVM的高潜伏期的主要来源，也是导致NVM高压操作的重要因素，这会影响其可靠性。我们提出了一个架构变化，其中每个长的位线在DRAM和NVM中被一个隔离晶体管分为两个段。一个细分市场可以用延迟和操作电压较低的访问。通过引入层，我们可以在每种内存类型（称为内存内置不对称）中启用非均匀访问，从而导致DRAM-NVM混合内存中的性能和可靠性权衡。我们通过三种方式扩展了现有的NVM-DRAM OS。首先，我们利用内存和内存的不对称性来分配和迁移DRAM和NVM层之间的存储页。其次，我们通过预测程序中新引用的内存页面的访问强度并将其放置在其初始分配期间的匹配层中来改进OS的页面分配决策。这可以最大程度地减少程序执行过程中的页面迁移，从而降低了性能开销。第三，我们提出了一种解决方案，以在相同内存的层次之间迁移页面，而无需通过存储器通道传输数据，从而最大程度地减少了通道的占用率并提高了性能。我们称之为Mneme的整体方法可以在DRAM-NVM混合层中启用和利用不对称性，可提高单核和多程序工作负载的性能和可靠性。
Modern computing systems are embracing hybrid memory comprising of DRAM and non-volatile memory (NVM) to combine the best properties of both memory technologies, achieving low latency, high reliability, and high density. A prominent characteristic of DRAM-NVM hybrid memory is that it has NVM access latency much higher than DRAM access latency. We call this inter-memory asymmetry. We observe that parasitic components on a long bitline are a major source of high latency in both DRAM and NVM, and a significant factor contributing to high-voltage operations in NVM, which impact their reliability. We propose an architectural change, where each long bitline in DRAM and NVM is split into two segments by an isolation transistor. One segment can be accessed with lower latency and operating voltage than the other. By introducing tiers, we enable non-uniform accesses within each memory type (which we call intra-memory asymmetry), leading to performance and reliability trade-offs in DRAM-NVM hybrid memory. We extend existing NVM-DRAM OS in three ways. First, we exploit both inter- and intra-memory asymmetries to allocate and migrate memory pages between the tiers in DRAM and NVM. Second, we improve the OS's page allocation decisions by predicting the access intensity of a newly-referenced memory page in a program and placing it to a matching tier during its initial allocation. This minimizes page migrations during program execution, lowering the performance overhead. Third, we propose a solution to migrate pages between the tiers of the same memory without transferring data over the memory channel, minimizing channel occupancy and improving performance. Our overall approach, which we call MNEME, to enable and exploit asymmetries in DRAM-NVM hybrid tiered memory improves both performance and reliability for both single-core and multi-programmed workloads.
