论文标题
超出保守限制：现代硬件利润的合并分析
Exceeding Conservative Limits: A Consolidated Analysis on Modern Hardware Margins
论文作者
论文摘要
现代的大规模计算系统（数据中心，超级计算机，云和边缘设置以及高端网络物理系统）采用异质体系结构，由多项CPU，通用多核GPU和可编程FPGA组成。这些体系结构的有效利用提出了几个挑战，其中主要是功耗。降压是减少芯片功耗的最有效方法之一。随着大型数据中心和其他大型计算基础架构中硬件加速器（即GPU和FPGA）的疾驰采用，可以使用对每个不同芯片的安全电压降低水平进行全面评估，以有效地降低总功率。我们介绍了现代CPU，GPU和FPGA的系统水平上降低电压率的最新研究调查。可以在所有设备中利用硅供应商插入的悲观电压防护板，以节省大量功率。平均而言，多核CPU的电压降低可达到12％，在许多核心GPU中，降压可以达到20％，而FPGA的电压可以达到39％。
Modern large-scale computing systems (data centers, supercomputers, cloud and edge setups and high-end cyber-physical systems) employ heterogeneous architectures that consist of multicore CPUs, general-purpose many-core GPUs, and programmable FPGAs. The effective utilization of these architectures poses several challenges, among which a primary one is power consumption. Voltage reduction is one of the most efficient methods to reduce power consumption of a chip. With the galloping adoption of hardware accelerators (i.e., GPUs and FPGAs) in large datacenters and other large-scale computing infrastructures, a comprehensive evaluation of the safe voltage reduction levels for each different chip can be employed for efficient reduction of the total power. We present a survey of recent studies in voltage margins reduction at the system level for modern CPUs, GPUs and FPGAs. The pessimistic voltage guardbands inserted by the silicon vendors can be exploited in all devices for significant power savings. On average, voltage reduction can reach 12% in multicore CPUs, 20% in manycore GPUs and 39% in FPGAs.
