论文标题
低硬件消耗，分辨率可配合的灰色代码振荡器在16nm，20nm和28nm fpGAS中实现的数字转换器
Low hardware consumption, resolution-configurable Gray code oscillator time-to-digital converters implemented in 16nm, 20nm and 28nm FPGAs
论文作者
论文摘要
本文介绍了低硬件消耗，可分辨率的，可自动校准灰色代码振荡器Xilinx 16nm Ultrascale+，20NM Ultrascale和28nm VirTex-7 firtex-7现场处理栅极阵列（FPGAS）中的灰色代码振荡器（TDC）。拟议的TDC有几项创新：1）一个采样矩阵以改善分辨率。 2）虚拟箱校准方法（VBCM）实现分辨率配置和自动校准。 3）标准FPGA设备中VBCM的硬件实现。我们在所有三个FPGA中实施并评估了16通道TDC系统。 Ultrascale+版本的最佳分辨率（最低显着位，LSB）为20.97 PS，0.09 LSB平均峰峰差异线性（DNLPK-PK）。 Ultrascale和Virtex-7版本分别以0.10 LSB平均DNLPK-PK和34.84 PS的最佳分辨率和0.08 LSB平均DNLPK-PK的最佳分辨率。
This paper presents a low hardware consumption, resolution-configurable, automatically calibrating Gray code oscillator time-to-digital converter (TDC) in Xilinx 16nm UltraScale+, 20nm UltraScale and 28nm Virtex-7 field-programmable gate arrays (FPGAs). The proposed TDC has several innovations: 1) a sampling matrix to improve the resolution. 2) a virtual bin calibration method (VBCM) to realize resolution configuration and automatic calibration. 3) a hardware implementation of the VBCM in standard FPGA devices. We implemented and evaluated a 16-channel TDC system in all three FPGAs. The UltraScale+ version achieved the best resolution (least significant bit, LSB) of 20.97 ps with 0.09 LSB averaged peak-peak differential linearity (DNLpk-pk). The UltraScale and Virtex-7 versions achieved the best resolutions of 36.01 ps with 0.10 LSB averaged DNLpk-pk and 34.84 ps with 0.08 LSB averaged DNLpk-pk, respectively.
