论文标题
使用等效的时序误差改进了对电流的DAC的分析
Improved Analysis of Current-Steering DACs Using Equivalent Timing Errors
论文作者
论文摘要
电流 - 驱动（CS）数字到Analog转换器（DAC）通过结合加权电流来源生成模拟信号。理想情况下，当前的源是同时在每个切换时合并的。但是，由于定时不匹配而在实践中并非如此，导致非线性失真。这项工作使用了以前工作引入的等效时间误差模型，以分析这些时间误差引起的信噪比（SDR）。使用行为模拟模型，我们证明我们的分析比以前的方法明显更准确。我们还使用仿真模型来研究定时不匹配在部分分段的CS-DAC中的效果，即由同样加权和二进制加权电流源组成的定时模型。
Current-steering (CS) digital-to-analog converters (DACs) generate analog signals by combining weighted current sources. Ideally, the current sources are combined at each switching instant simultaneously. However, this is not true in practice due to timing mismatch, resulting in nonlinear distortion. This work uses the equivalent timing error model, introduced by previous work, to analyze the signal-to-distortion ratio (SDR) resulting from these timing errors. Using a behavioral simulation model we demonstrate that our analysis is significantly more accurate than the previous methods. We also use our simulation model to investigate the effect of timing mismatch in partially-segmented CS-DACs, i.e., those comprised of both equally-weighted and binary-weighted current sources.
