论文标题
缩放相对图的电路模型还原
Circuit Model Reduction with Scaled Relative Graphs
论文作者
论文摘要
持续的分数是复杂对象的经典表示（例如，实数）作为简单对象的总和和倒置（例如，整数）。线性电路理论中的类比是一系列串联/平行的单端口：端口行为是持续的分数，其中包含其元素的端口行为。截断持续的分数是一种经典的近似方法，它对应于从端口删除最远的电路元素。我们将此想法应用于由任意非线性关系组成的串联/平行单端口的链条。这提供了一种模型还原方法，该方法自动保留诸如增量阳性之类的属性。缩放的相对图（SRG）给出了原始端口行为和截断的端口行为的图形表示。这些SRG的差异给出了近似误差的结合，这证明与现有方法具有竞争力。
Continued fractions are classical representations of complex objects (for example, real numbers) as sums and inverses of simpler objects (for example, integers). The analogy in linear circuit theory is a chain of series/parallel one-ports: the port behavior is a continued fraction containing the port behaviors of its elements. Truncating a continued fraction is a classical method of approximation, which corresponds to deleting the circuit elements furthest from the port. We apply this idea to chains of series/parallel one-ports composed of arbitrary nonlinear relations. This gives a model reduction method which automatically preserves properties such as incremental positivity. The Scaled Relative Graph (SRG) gives a graphical representation of the original and truncated port behaviors. The difference of these SRGs gives a bound on the approximation error, which is shown to be competitive with existing methods.
