论文标题
蒙特·西蒙恩（Monte Cimone）：为第一代RISC-V高性能计算机铺平道路
Monte Cimone: Paving the Road for the First Generation of RISC-V High-Performance Computers
论文作者
论文摘要
新的开放式和免版税的RISC-V ISA吸引了整个计算连续性的兴趣，从微控制器到超级计算机。已经宣布了高性能RISC-V处理器和加速器，但是基于RISC-V的HPC系统将需要整体共同设计，跨越内存，存储层次结构互连和完整的软件堆栈。在本文中，我们描述了基于U740的完全运营的多层计算机原型和硬件软件测试床，这是一种双重精神，可双精度的多核，64位RISC-RISC-V SOC。 Monte Cimone并非旨在实现强大的浮点性能，而是建立的目的是“启动管道”，并探索整合多节点RISC-V群集的挑战，能够在RISC-V硬件上提供HPC生产堆栈，包括互连，存储，存储和电源监控。我们介绍了硬件/软件集成工作的结果，该工作表明了软件和硬件准备和成熟度的显着水平 - 表明RISC -V HPC机器的第一代可能不会在将来还不到。
The new open and royalty-free RISC-V ISA is attracting interest across the whole computing continuum, from microcontrollers to supercomputers. High-performance RISC-V processors and accelerators have been announced, but RISC-V-based HPC systems will need a holistic co-design effort, spanning memory, storage hierarchy interconnects and full software stack. In this paper, we describe Monte Cimone, a fully-operational multi-blade computer prototype and hardware-software test-bed based on U740, a double-precision capable multi-core, 64-bit RISC-V SoC. Monte Cimone does not aim to achieve strong floating-point performance, but it was built with the purpose of "priming the pipe" and exploring the challenges of integrating a multi-node RISC-V cluster capable of providing an HPC production stack including interconnect, storage and power monitoring infrastructure on RISC-V hardware. We present the results of our hardware/software integration effort, which demonstrate a remarkable level of software and hardware readiness and maturity - showing that the first generation of RISC-V HPC machines may not be so far in the future.
