论文标题
爱丽丝：EFPGA修复的自动设计流
ALICE: An Automatic Design Flow for eFPGA Redaction
论文作者
论文摘要
对于许多半导体设计房屋来说，制造集成电路变得无法承受。将制造物外包给第三方铸造厂需要保护硬件设计的知识产权的方法。设计人员可以依靠嵌入式的可重构设备来完全隐藏所选设计部分的真实功能，除非提供了配置字符串（Bitstream）。但是，选择此类部分并创建相应的可重构面料仍然是开放的问题。我们提出了爱丽丝（Alice），这是一种解决此问题EDA挑战的设计流。爱丽丝将一种或多种可重构面料与电路的其余部分之间的RTL模块划分，使相应的编辑设计的生成自动化。
Fabricating an integrated circuit is becoming unaffordable for many semiconductor design houses. Outsourcing the fabrication to a third-party foundry requires methods to protect the intellectual property of the hardware designs. Designers can rely on embedded reconfigurable devices to completely hide the real functionality of selected design portions unless the configuration string (bitstream) is provided. However, selecting such portions and creating the corresponding reconfigurable fabrics are still open problems. We propose ALICE, a design flow that addresses the EDA challenges of this problem. ALICE partitions the RTL modules between one or more reconfigurable fabrics and the rest of the circuit, automating the generation of the corresponding redacted design.
