论文标题
节能深度尖峰神经网络处理器设计的跨度尖峰编码和转换培训
A Time-to-first-spike Coding and Conversion Aware Training for Energy-Efficient Deep Spiking Neural Network Processor Design
论文作者
论文摘要
在本文中，我们提出了一种节能的SNN体系结构，该体系结构可以通过提高的精度无缝地运行深度尖峰神经网络（SNN）。首先，我们提出了一个转换意识培训（CAT），以减少无硬件实施开销而无需安排SNN转换损失。在拟议的CAT中，用于在ANN训练过程中开发用于模拟SNN的激活函数有效利用以减少转化后数据表示误差。基于CAT技术，我们还提出了一项跨度尖峰编码，该编码可以通过使用SPIKE时间信息来轻巧计算。支持提出技术的SNN处理器设计已使用28nm CMOS流程实施。该处理器的推理能量分别为91.7％，67.9％和57.4％的TOP-1精确度，分别为486.7UJ，503.6UJ和1426UJ，分别处理CIFAR-10，CIFAR-100和TINY-IMIGENET，当时运行VGG-16的vgg-16具有5bit sogarithmic sogarithmic sogarithmic rategarithmic sovernation。
In this paper, we present an energy-efficient SNN architecture, which can seamlessly run deep spiking neural networks (SNNs) with improved accuracy. First, we propose a conversion aware training (CAT) to reduce ANN-to-SNN conversion loss without hardware implementation overhead. In the proposed CAT, the activation function developed for simulating SNN during ANN training, is efficiently exploited to reduce the data representation error after conversion. Based on the CAT technique, we also present a time-to-first-spike coding that allows lightweight logarithmic computation by utilizing spike time information. The SNN processor design that supports the proposed techniques has been implemented using 28nm CMOS process. The processor achieves the top-1 accuracies of 91.7%, 67.9% and 57.4% with inference energy of 486.7uJ, 503.6uJ, and 1426uJ to process CIFAR-10, CIFAR-100, and Tiny-ImageNet, respectively, when running VGG-16 with 5bit logarithmic weights.
