论文标题

确定性故障连通性标记方案

Deterministic Fault-Tolerant Connectivity Labeling Scheme

论文作者

Izumi, Taisuke, Emek, Yuval, Wadayama, Tadashi, Masuzawa, Toshimitsu

论文摘要

The \emph{$f$-fault-tolerant connectivity labeling} ($f$-FTC labeling) is a scheme of assigning each vertex and edge with a small-size label such that one can determine the connectivity of two vertices $s$ and $t$ under the presence of at most $f$ faulty edges only from the labels of $s$, $t$, and the faulty edges.本文提出了一种新的确定性$ f $ -FTC标签方案,达到$ o(f^2 \ mathrm {polylog}(n))$ - 位标签大小和一个多项式构造时间,解决了Dory and Parter [PODC'21]留下的开放问题。我们构建的关键要素是通过与错误校正代码理论的某种自然联系来开发Ahn,Guha和McGreger [Soda'12]的图形草图技术的确定性对应物。这项技术消除了Dory-Parter方案的杂物化的一个主要障碍。整个方案是通过将此技术与从开创性$ε$ -NET理论得出的新的确定性图稀疏算法相结合来获得的,该算法也具有独立的兴趣。作为副产品,我们的结果推断出具有非平凡性能保证和改进确定性的耐断层紧凑路由的第一个确定性耐受性距离标记方案。作者认为,我们的新技术在将来对基于图形草图的更有效的FTC标签方案和其他相关应用程序的探索中可能有用。

The \emph{$f$-fault-tolerant connectivity labeling} ($f$-FTC labeling) is a scheme of assigning each vertex and edge with a small-size label such that one can determine the connectivity of two vertices $s$ and $t$ under the presence of at most $f$ faulty edges only from the labels of $s$, $t$, and the faulty edges. This paper presents a new deterministic $f$-FTC labeling scheme attaining $O(f^2 \mathrm{polylog}(n))$-bit label size and a polynomial construction time, which settles the open problem left by Dory and Parter [PODC'21]. The key ingredient of our construction is to develop a deterministic counterpart of the graph sketch technique by Ahn, Guha, and McGreger [SODA'12], via some natural connection with the theory of error-correcting codes. This technique removes one major obstacle in de-randomizing the Dory-Parter scheme. The whole scheme is obtained by combining this technique with a new deterministic graph sparsification algorithm derived from the seminal $ε$-net theory, which is also of independent interest. As byproducts, our result deduces the first deterministic fault-tolerant approximate distance labeling scheme with a non-trivial performance guarantee and an improved deterministic fault-tolerant compact routing. The authors believe that our new technique is potentially useful in the future exploration of more efficient FTC labeling schemes and other related applications based on graph sketches.

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