论文标题
使用现场可编程阵列在连贯的光传输系统中实现基于神经网络的均衡器
Implementing Neural Network-Based Equalizers in a Coherent Optical Transmission System Using Field-Programmable Gate Arrays
论文作者
论文摘要
在这项工作中,我们演示了相干光学传输系统中反复和前馈神经网络(NN)基于非线性补偿的离线FPGA实现。首先,我们提出了一个实现管道,显示了模型从Python库转换为FPGA芯片合成和实现。然后,我们回顾了非线性激活功能硬件实现的主要替代方法。主要结果分为三个部分:性能比较,如何实现激活功能的分析以及有关硬件复杂性的报告。 Q因子的性能是针对双向长短记忆的情况,再加上卷积NN(BILSTM + CNN)均衡器,CNN均衡器和标准的1-STPS数字后反射(DBP),用于模拟和实验的单个通道双极化(SC-DP)的模拟和实验繁殖(scd-dp)16QM 17 QBD。与实验数据集中的色散补偿基线相比,Bilstm+CNN均衡器提供了与DBP相似的结果和1.7 dB Q因子的增益。之后,我们使用泰勒系列,分段线性和查找表(LUT)近似值来评估Q因子和硬件利用的影响。我们还展示了如何通过额外的训练来减轻近似错误,并提供一些有关LUT近似可能梯度问题的见解。最后,为了评估硬件实现的复杂性,以实现200G和400G吞吐量,在FPGA中开发和实现了具有近似激活功能的基于近似激活功能的基于固定点的均衡器。
In this work, we demonstrate the offline FPGA realization of both recurrent and feedforward neural network (NN)-based equalizers for nonlinearity compensation in coherent optical transmission systems. First, we present a realization pipeline showing the conversion of the models from Python libraries to the FPGA chip synthesis and implementation. Then, we review the main alternatives for the hardware implementation of nonlinear activation functions. The main results are divided into three parts: a performance comparison, an analysis of how activation functions are implemented, and a report on the complexity of the hardware. The performance in Q-factor is presented for the cases of bidirectional long-short-term memory coupled with convolutional NN (biLSTM + CNN) equalizer, CNN equalizer, and standard 1-StpS digital back-propagation (DBP) for the simulation and experiment propagation of a single channel dual-polarization (SC-DP) 16QAM at 34 GBd along 17x70km of LEAF. The biLSTM+CNN equalizer provides a similar result to DBP and a 1.7 dB Q-factor gain compared with the chromatic dispersion compensation baseline in the experimental dataset. After that, we assess the Q-factor and the impact of hardware utilization when approximating the activation functions of NN using Taylor series, piecewise linear, and look-up table (LUT) approximations. We also show how to mitigate the approximation errors with extra training and provide some insights into possible gradient problems in the LUT approximation. Finally, to evaluate the complexity of hardware implementation to achieve 200G and 400G throughput, fixed-point NN-based equalizers with approximated activation functions are developed and implemented in an FPGA.